As an example of an apparatus for testing a plurality of uncut integrated circuits formed in a wafer at one time or separately in several batches, there is one using a chip unit having: a chip support and a plurality of test chips arranged on the upside of the chip support; a probe unit distanced downward from the chip unit and having a probe support and a plurality of contacts arranged on the underside of the probe support; and a connection unit disposed between the chip unit and the probe unit and provided with a pin support and a plurality of connection pins which penetrate the pin support vertically and whose upper ends and lower ends can project upward and downward of the pin support (Japanese National Patent Appln. Public Disclosure No. 10-510682 and No. 11-251383, which are incorporated by reference).
In the above prior art, each test chip generates an electrical signal for use in an electrical test of an integrated circuit, i.e., a device under test and has a function to process a response signal upon receipt of the response signal from the device under test. Thus, since the prior art does not require a plurality of wiring boards with a plurality of circuits which have a function of the test chips, a test head required before the prior art is remarkably minimized, so that the testing apparatus becomes less expensive.
The above conventional technique, however, merely stacks a chip unit, a probe unit and a connection unit in their thickness direction, and neither combines those three units nor have a support unit support the three units.
The present invention aims to couple at least one of the chip unit and the probe unit, and the connection unit so that the relative force between them can be adjusted.